| CODE | MNE3002 | ||||||||||||||||||||
| TITLE | Hardware Description Languages | ||||||||||||||||||||
| UM LEVEL | 03 - Years 2, 3, 4 in Modular Undergraduate Course | ||||||||||||||||||||
| MQF LEVEL | 6 | ||||||||||||||||||||
| ECTS CREDITS | 5 | ||||||||||||||||||||
| DEPARTMENT | Microelectronics and Nanoelectronics | ||||||||||||||||||||
| DESCRIPTION | Objectives: The study-unit introduces hardware description languages VHDL and Verilog as tools for describing and synthesizing logic circuits in the process of digital design automation. During the lab sessions, the students will familiarise themselves with the process of digital integrated circuit synthesis, together with place and route, starting from HDL code to silicon/gate array level. Syllabus: - VHDL and Verilog, functional and structural descriptions, simulation, synthesis, FPGA programming, place and route for IC masks, post layout timing simulation; - Introduction to the design methodology using hardware description languages. Structural, concurrent and sequential VHDL descriptions, subprograms, VHDL operators, signals and variables, variable types, WAIT statements and sensitivity lists; - Simulation of VHDL/Verilog models, test benches, debugging - outputting to the console. Design organisiation and parameterisation: subprograms, packages, default, fixed and generic parameters, design configuration general purpose test benches; - Delay modeling and timing issues. Dataflow description in VHDL/Verilog: multiplexers, Moore and Mealy FSMs, open collector gates; - Synthesis, timing constraints, pad-mapping, post-synthesis (timing) simulation, FPGA programming. Laboratory Work: - Design and implementation of a digital circuit starting from a HDL description using Xilinx XC4000X FPGA chips. Learning Outcomes: 1. Knowledge & Understanding: By the end of the study-unit, the students will be able to: • Understand and read VHDL and Verilog syntax; • Understand and analyse test bench syntax and interpret simulation results; • Familiarise themselves with FPGA internals and be able to understand how VHDL code into FPGA circuitry. 2. Skills: By the end of the study-unit, the students will be able to: • Design and write VHDL code, which implement combinational and sequential logic circuits; • Synthesise VHDL code onto FPGAs and interface the FPGA to external electronic circuitry; • Troubleshoot VHDL code after analyzing simulation results and measuring outputs from FPGA modules. Textbook: - Roth Charles H., John Lizy Kurian, Digital Systems Design Using VHDL, Thomson, ISBN 978-0-495-24470-7 Reading List: - Ciletti, Advanced Digital Design with Verilog HDL, Prentice Hall, 0-13-089161-4 |
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| RULES/CONDITIONS | Before TAKING THIS UNIT YOU ARE ADVISED TO TAKE CCE1013 AND TAKE CCE1014 | ||||||||||||||||||||
| STUDY-UNIT TYPE | Lecture and Tutorial | ||||||||||||||||||||
| METHOD OF ASSESSMENT |
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| LECTURER/S | Edward Gatt (Co-ord.) |
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The University makes every effort to ensure that the published Courses Plans, Programmes of Study and Study-Unit information are complete and up-to-date at the time of publication. The University reserves the right to make changes in case errors are detected after publication.
The availability of optional units may be subject to timetabling constraints. Units not attracting a sufficient number of registrations may be withdrawn without notice. It should be noted that all the information in the description above applies to study-units available during the academic year 2024/5. It may be subject to change in subsequent years. |
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