| CODE | MNE5113 | ||||||||||||
| TITLE | System on Chip | ||||||||||||
| UM LEVEL | 05 - Postgraduate Modular Diploma or Degree Course | ||||||||||||
| MQF LEVEL | 7 | ||||||||||||
| ECTS CREDITS | 5 | ||||||||||||
| DEPARTMENT | Microelectronics and Nanoelectronics | ||||||||||||
| DESCRIPTION | This unit covers helps students how processor architectures are implemented in hardware. The topics covered include different processing building blocks including: • The use of IP cores to implement processor hardware; • Implementing Hardware required for different Buses protocols including peripheral buses, packet networks, pipelined buses; • The use of Memory Sharing; • Implementing DMA controllers and Bridge Architectures; • Designing Microcontroller architectures, with HDL and SystemC; • Designing Microcontroller architectures RISC and CISC architectures through the implementation of controller building blocks including the ALU, the control unit, memory/cache registers, sleep modes (low power modes), and interrupt handling; • Optimisation of processor design according to Speed / Area / Power consumption requirements; • Implementing I/O interfaces using HDL including UART, parallel port, SPI, Ethernet, USB, CAN bus. MMC card interfacing; • Overview of the different implementation techniques of processors on FPGA platform using HDL; • Design of Mixed-mode circuits SOC and SIP; • Overview of Chip-to-chip synchronization and communication issues; • Overview of Bonding and Packaging issues, production yield issues. Study-unit Aims: The unit aims at teaching concepts of how processors can be implemented using hardware description languages. Optimization techniques of different arithmetic units are presented. Learning Outcomes: 1. Knowledge & Understanding: By the end of the study-unit the student will be able to: • Understand the basic building blocks used to implement a processor chip and how these will interact together to create a dedicated processor, which is capable of implementing the required task; • Optimize hardware circuitry to meet design specifications including: high speed design, low power design and low chip areas; • Be able to integrate different processor units into system-on-chip processors, while outlining how these processor units can communicate together to handle tasks. 2. Skills: By the end of the study-unit the student will be able to: • Design simple and more complex processors including communication interfaces and bus links using HDL; • Implement processor FPGA/ASIC designs that meeting system specifications; • Use IP Cores to implement processor architectures, that are capable of implementing tasks. Textbooks: • W. Wolf, “Modern VLSI Design: System-on-Chip Design”, 3rd edition,Prentice Hall, 2002 • Farzad Nekoogar and Faranak Nekoogar, “From ASICS to SOCs: A Practical Approach”, 1st edition, Prentice Hall, 2003 • Buchanan, Wilson, Advanced PC Architecture, Addison-Wesley, 0-201-39858-3 • Stallings, Computer Organisation and Architecture Designing for Performance, Prentice Hall, 0-13-359985-X |
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| RULES/CONDITIONS | Before TAKING THIS UNIT YOU ARE ADVISED TO TAKE MNE3002 | ||||||||||||
| STUDY-UNIT TYPE | Lecture and Tutorial | ||||||||||||
| METHOD OF ASSESSMENT |
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| LECTURER/S | Edward Gatt |
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The University makes every effort to ensure that the published Courses Plans, Programmes of Study and Study-Unit information are complete and up-to-date at the time of publication. The University reserves the right to make changes in case errors are detected after publication.
The availability of optional units may be subject to timetabling constraints. Units not attracting a sufficient number of registrations may be withdrawn without notice. It should be noted that all the information in the description above applies to study-units available during the academic year 2024/5. It may be subject to change in subsequent years. |
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