VHDL code generator for digital filter implementation

Abstract

Digital filters are of great importance to the signal processing world, as these systems are widely used in different areas of this field, ranging from communication systems to video and image processing. Digital filters are systems designed to modify a digital signal. Once these systems are designed and the filter coefficients are obtained, implementation can be done in a number of structures which ultimately produce the same output signal. Field programmable gate arrays (FPGA) are programmable chips which in recent years have gained popularity in the implementation of digital signal processing (DSP) applications, thanks to their high speed and reconfigurability. FPGAs can be programmed in hardware description languages such as VHDL. Thus, in this final year project (FYP), we develop a tool in Python capable of generating files which contain VHDL filter implementations synthesisable on any FPGA. After obtaining filter coefficients using MATLAB, the code generator is able to realise filters in four different structures and generate other VHDL modules which can be used for simulation and testing purposes. Twenty different filter implementations are generated using the presented software. After simulations in ModelSim, the resultant output signals are compared to theoretical results, where correct filtering computation is verified. Furthermore, the implementations are synthesised using Xilinx Synthesis Tool (XST) to obtain measurements about the speed and area efficiency of the VHDL code generated by the presented tool. Synthesis results are used to compare the structures explored in this study. The presented tool is also compared to MATLAB’s Filter Builder where synthesis results show that both code generators follow the same trends in terms of the speed and area efficiency of each filtering structure. Furthermore, these results show that distributed arithmetic structures are implemented more efficiently by MATLAB, while faster multiply-accumulate structures are generated by the presented tool.