High performance CMOS frequency synthesis architectures for microwave applications

Abstract

The motivation of this research was to investigate novel low voltage microwave frequency synthesizer architectures which can provide a wide range of frequencies with an acceptable phase noise response, integrated spurious level and power consumption as required by modem communication systems. In particular the work undertaken and described in this dissertation can be classified into three main parts. The first part reports the study, design and silicon implementation of a low voltage 1.6 GHz quadrature output integer-N phase locked loop based frequency synthesizer with an on-chip regulated DC-DC converter in order to achieve a wide tuning range with negligible effect on the phase noise and spurious level. The second part discusses the investigation of the use of a Micro-electro-mechanical Systems (MEMS) based tuneable inductor both as a means to extend the frequency tuning range and also to facilitate and improve the voltage-controlled oscillator design in terms of phase noise response and power consumption in comparison to a design based on conventional capacitive tuning. Finally, the last part of the dissertation discusses the investigation of the spurious tone levels in novel digitally based frequency synthesis architectures for an Ultra Wideband MB-OFDM (Multi-band Orthogonal Frequency Division Multiplexing) Alliance application which requires a wide range of frequencies. Architectures are proposed as low silicon area alternatives to state-of-the-art solutions.