Please use this identifier to cite or link to this item:
https://www.um.edu.mt/library/oar/handle/123456789/108836| Title: | A low voltage high resolution pipelined incremental ADC |
| Authors: | Grech, Ivan Micallef, Joseph Maloberti, Franco Azzopardi, George |
| Keywords: | Low voltage systems Capacitors Analog-to-digital converters Microelectronics |
| Issue Date: | 1999 |
| Publisher: | Institute of Electrical and Electronics Engineers |
| Citation: | Azzopardi, G., Grech, I., Micallef, J., & Maloberti, F. (1999). A low voltage high resolution pipelined incremental ADC. 6th IEEE International Conference on Electronics, Circuits and Systems, Paphos. 1499-1502. |
| Abstract: | A low voltage incremental analog-to-digital converter with a pipelined architecture is presented. Using first order modulators the conversion time is significantly reduced even at low sampling rates while maintaining high resolution. The switched capacitor converter is designed to operate with a 1.8 V power supply and uses three pipelined modulators. With careful design and digital correction it is possible to achieve more than 15 bit resolution. |
| URI: | https://www.um.edu.mt/library/oar/handle/123456789/108836 |
| Appears in Collections: | Scholarly Works - FacICTMN |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| A_low_voltage_high_resolution_pipelined_incremental_ADC.pdf Restricted Access | 636.17 kB | Adobe PDF | View/Open Request a copy |
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