Implementation of an I2C interface on an FPGA

Abstract

The need to communicate from a ‘master’ to a ‘slave’ in a microcontroller system has been the catalyst for the creation of the Inter Integrated-Circuit Communication protocol. The main attraction of this protocol is the use of two lines for sending and receiving data to and from peripherals. Pin out conservation has been an issue back in the eighties and became more prominent when integration scales continue to increase. This fact could be one of the reasons why this protocol remained popular over time. With the increase of devices using various technologies, communication between such devices can be handled by this protocol. FPGA’s are no exception and the design of a module accomplishing this task is the target of this project. Field Programmable Gate Arrays are gaining ground with respect to other growing technologies, mainly because of the possibility of obtaining real parallel processing and therefore gaining speed for real-time applications. Although the I2C protocol is a moderately high speed serial protocol, though not the fastest speed communication, it can serve as a means of communication with slow peripherals designed to communicate with this protocol. This project will address two side issues apart from obtaining the functionality of the bus. Particular attention is given to noise immunity and to the footprint occupied by the module.