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https://www.um.edu.mt/library/oar/handle/123456789/116505
Title: | Implementation of a sudoku puzzle solver on a FPGA |
Authors: | Ciantar, Keith George Casha, Owen |
Keywords: | Sudoku Puzzles Field programmable gate arrays Probabilities Information technology Testing Puzzles -- Software |
Issue Date: | 2023 |
Publisher: | Institute of Electrical and Electronics Engineers |
Citation: | Ciantar, K. G., & Casha, O. (2023, July). Implementation of a Sudoku Puzzle Solver on a FPGA. International Conference on Control, Decision and Information Technologies (CoDIT), Italy. 1803-1808. |
Abstract: | In this paper, the design, implementation and evaluation of a hybrid Sudoku puzzle solver on a Field-Programmable Gate Array (FPGA) is presented. The solver initially makes use of pen-and-paper solving techniques to reduce the number of possible values and prune the overall search space. Once this process is complete, the solver then utilizes a depth-first search algorithm to systematically guess and backtrack through the puzzle, until a solution is reached. This work strived to implement a solver with minimal area utilization while maintaining simplicity and still achieving adequate performance. The implementation and the testing of the Sudoku puzzle solver were carried out on a Xilinx Spartan-6 XC6SLX45 FPGA. |
URI: | https://www.um.edu.mt/library/oar/handle/123456789/116505 |
Appears in Collections: | Scholarly Works - FacICTMN |
Files in This Item:
File | Description | Size | Format | |
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Implementation_of_a_sudoku_puzzle_solver_on_a_FPGA(2023).pdf Restricted Access | 2.26 MB | Adobe PDF | View/Open Request a copy |
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