Configurable soft microprocessor on FPGA

Abstract

Processors today have become prevalent in a multitude of electronic circuits. They are known conventionally as IC chips that have been fabricated using Silicon technology. There exists on the other another variety called “soft” processors. These soft cores are abstract and generalized software designs of an actual processor usually coded in an HDL (Hardware Description Language). Later on these cores can be synthesized and then implemented using a variety of programmable media, in this case FPGAs. The project‟s goal was to enhance the capabilities of an 8-bit microcontroller, provided at the onset of the project, by changing some of its core characteristics or by adding several components. Several of the changes implemented were altering the widths of the datapath and the data bus from 8 to 16-bit. These two properties came to determine what was called the Mode of Operation of the core which determined the specific sequence of steps taken required to execute a program which in turn affected the speed of the core and the specific format of the code understood by the core. Later on other areas of the core were developed such as expanding the Instruction Set of the processor and appending optional components such as multipliers and dividers for each mode. This soft processor also had a simple GUI designed to facilitate configuring the core according to a user‟s specifications. . To analyze the final utility and successful design of the processor required a continuous amount of simulations for each appended feature which later required implementing and later testing the core itself on a Virtex-5 FPGA development board using the Xilinx ISE suite. This later prompted an analysis of the core‟s utilization of resources on the FPGA chip and the performance of each of the core‟s modes. With regards to resource utilization, the more notable configurations of the Modifix core were compared between each other, along with other off-the-shelf 8-bit soft cores, using metrics such as the number of LUT-FF pairs and Slices utilized. Analysis of the performance of the core was maintained between the different modes of the core by executing a series of programs and comparing the execution time taken.