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DC Field | Value | Language |
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dc.date.accessioned | 2016-09-13T08:09:42Z | |
dc.date.available | 2016-09-13T08:09:42Z | |
dc.date.issued | 2016 | |
dc.identifier.uri | https://www.um.edu.mt/library/oar//handle/123456789/12243 | |
dc.description | B.ENG.(HONS) | en_GB |
dc.description.abstract | Applications such as communications, and strain/margin testing require generation of arbitrary waveforms with fast frequency switching and low frequency resolution. Direct Digital Synthesis (DDS) is a method that can be used to generate such arbitrary waveforms. This Dissertation looks at the design, development and testing of a DDS Arbitrary Function Generator (AFG). The DDS core was developed on an Artix 7 Field Programmable Gate Array (FPGA). Simply put, the DDS core consists of a 47-bit phase accumulator; thus obtaining a frequency resolution of 19:2 μHz, and a look-up table containing 16,384 sample points that are used to generate the output waveform. Connected to the DDS core is a Digital to Analogue Converter (DAC) that converts the digital signal into an analogue current. A 2.7Gsps DAC is used, offering 11 bits of output resolution. The developed AFG has a 600MHz bandwidth and a 505 ps rise time. Furthermore a maximum Narrowband Spurious Free Dynamic Range (NSFDR) of -56dBc and a maximum Wideband Spurious Free Dynamic Range (WSFDR) of -31.5dBc were obtained. Additionally, a maximum phase noise of - 77.5dBc/Hz at a frequency offset of 20 kHz was achieved. Finally the control of the AFG was provided through the development of the Graphical User Interface (GUI). The features available through this interface include the changing of the frequency and the waveform of the output signal. | en_GB |
dc.language.iso | en | en_GB |
dc.rights | info:eu-repo/semantics/restrictedAccess | en_GB |
dc.subject | Field programmable gate arrays | en_GB |
dc.subject | Graphical user interfaces (Computer systems) | en_GB |
dc.subject | Electric generators | en_GB |
dc.title | Direct digital synthesis radio frequency arbitrary function generator using an FPGA | en_GB |
dc.type | bachelorThesis | en_GB |
dc.rights.holder | The copyright of this work belongs to the author(s)/publisher. The rights of this work are as defined by the appropriate Copyright Legislation or as modified by any successive legislation. Users may access this work and can make use of the information contained in accordance with the Copyright Legislation provided that the author must be properly acknowledged. Further distribution or reproduction in any format is prohibited without the prior permission of the copyright holder. | en_GB |
dc.publisher.institution | University of Malta | en_GB |
dc.publisher.department | Faculty of Engineering. Department of Electronic Systems Engineering | en_GB |
dc.description.reviewed | N/A | en_GB |
dc.contributor.creator | Mifsud, Andrea | |
Appears in Collections: | Dissertations - FacEng - 2016 Dissertations - FacEngESE - 2016 |
Files in This Item:
File | Description | Size | Format | |
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16BENGEE020.pdf Restricted Access | 30.49 MB | Adobe PDF | View/Open Request a copy |
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