Development of front-end readout electronics system for the ALICE HMPID and charged-particle veto detectors

Abstract

Luminosity of lead-ion collisions at the Large Hadron Collider will be increased in the forthcoming Run 3 to 6×1027 cm2s-1, corresponding to an average inelastic interaction rate of 50 kHz. At the same time, paradigm of data taking of the ALICE experiment changes aiming to collect and process all interaction data, which represents an increase in data sample rate by two orders of magnitude with respect to the present system. This requirement demands a reliable readout electronic system with an increase in data bandwidth, strict timing constraints, and low power consumption. This work presents the hardware architecture of a newly developed front-end readout electronic system for the Charged-Particle Veto detector, located in the Photo Spectrometer at the A Large Ion Collider Experiment situated at the largest European facility for Nuclear Research, CERN. The developed front-end hardware architecture enables the simultaneous readout of 23,040 cathode pad channels for amplitude analysis, contributing a ten-fold increase in bandwidth when compared to prior system. Main contributions to this achievement include the re-design of highly dense interconnect printed circuit boards, use of 3.125 Gbps data links and the implementation of a radiation tolerant firmware architecture using low power 28 nm field programmable gate arrays. Measurement results indicate that the newly developed data acquisition electronic system satisfies the target detector readout rate requirements. This paper discusses the firmware and hardware implementation details, followed by the presentation of the performance measurement results for the recently developed Charged-Particle Veto detector front-end readout topology when compared to other particle detector electronic systems.