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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Bonnici, Mark | - |
| dc.contributor.author | Gatt, Edward | - |
| dc.contributor.author | Micallef, Joseph | - |
| dc.contributor.author | Grech, Ivan | - |
| dc.date.accessioned | 2017-03-20T09:49:36Z | - |
| dc.date.available | 2017-03-20T09:49:36Z | - |
| dc.date.issued | 2006 | - |
| dc.identifier.citation | Bonnici, M., Gatt, E., Micallef, J., & Grech, I. (2006). Artificial neural network optimization for FPGA. 13th IEEE International Conference on Electronics, Circuits and Systems, Nice. 1340-1343. | en_GB |
| dc.identifier.uri | https://www.um.edu.mt/library/oar//handle/123456789/17632 | - |
| dc.description.abstract | This paper describes a cost effective artificial neural network implementation on an FPGA in three easy steps. Furthermore, it proposes the manner in which network layers are mapped into a particular hardware structure such that the performance and efficiency, with which the hardware resources are used, are greatly improved. A reconfigurable, parameterised neural node is presented as the basic building block for neural implementations, and is modelled in Verilog (HDL). The results show a high degree of parallelism, fast performance and most important low area resources. | en_GB |
| dc.language.iso | en | en_GB |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_GB |
| dc.rights | info:eu-repo/semantics/restrictedAccess | en_GB |
| dc.subject | Field programmable gate arrays | en_GB |
| dc.subject | Neural networks (Computer science) | en_GB |
| dc.subject | Computer hardware description languages | en_GB |
| dc.title | Artificial neural network optimization for FPGA | en_GB |
| dc.type | conferenceObject | en_GB |
| dc.rights.holder | The copyright of this work belongs to the author(s)/publisher. The rights of this work are as defined by the appropriate Copyright Legislation or as modified by any successive legislation. Users may access this work and can make use of the information contained in accordance with the Copyright Legislation provided that the author must be properly acknowledged. Further distribution or reproduction in any format is prohibited without the prior permission of the copyright holder. | en_GB |
| dc.bibliographicCitation.conferencename | 13th IEEE International Conference on Electronics, Circuits and Systems | en_GB |
| dc.bibliographicCitation.conferenceplace | Nice, France, 10-13/12/2006 | en_GB |
| dc.description.reviewed | peer-reviewed | en_GB |
| dc.identifier.doi | 10.1109/ICECS.2006.379730 | - |
| Appears in Collections: | Scholarly Works - FacICTMN | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Artificial Neural Network Optimization for FPGA.pdf Restricted Access | Artificial neural network optimization for FPGA | 276.81 kB | Adobe PDF | View/Open Request a copy |
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