The implementation of the SATA protocol on an FPGA

Abstract

The MEMENTO (Multi camEra high fraMe ratE syNchronisaTion) is an initiative at commercialising a high speed multi-camera system. A system which will require enormous amount of data transfers between the camera devices and storage hub. All information transfer is done via serial transceivers, with a minimum of eight transceiver lines each capable of handling 10Gb/s transfer rates. In light of this, this final year project aims at solving and providing solutions regarding the data storage assignment. Serial ATA is the chosen protocol which will be used for meeting the requirements. The latest version, SATA III, can reach speeds up to 6Gb/s. A SATA core is to be implemented on an FPGA and tested on various storage devices. Most of the work was directed towards the bottom layers of the core, mainly in the underlying transceivers conducting all the differential signalling. The work is implemented on a Xilinx Artix 7 device for development purposes which will eventually be migrated to a larger Ultrascale device.