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dc.contributor.authorDobinson, Robert W.-
dc.contributor.authorHaas, Stefan-
dc.contributor.authorKorcyl, Krzysztof M.-
dc.contributor.authorLevine, Michael J.-
dc.contributor.authorLokier, J.-
dc.contributor.authorMartin, Brian M.-
dc.contributor.authorMeirosu, Catalin-
dc.contributor.authorSaka, F.-
dc.contributor.authorVella, Kevin-
dc.date.accessioned2018-03-22T10:07:31Z-
dc.date.available2018-03-22T10:07:31Z-
dc.date.issued2001-
dc.identifier.citationDobinson, R. W., Haas, S., Korcyl, K., LeVine, M. J., Lokier, J., Martin, B.,...Vella, K. (2001). Testing and modeling ethernet switches and networks for use in ATLAS high-level triggers. IEEE Transactions on Nuclear Science, 48(3 I), 607-612.en_GB
dc.identifier.urihttps://www.um.edu.mt/library/oar//handle/123456789/28137-
dc.description.abstractThe ATLAS second level trigger will use a multilayered LAN network to transfer 5 Gbyte/s detector data from /spl sim/1500 buffers to a few hundred processors. A model of the network has been constructed to evaluate its performance. A key component of the network model is a model of an individual switch, reproducing the behavior measured in real devices. A small number of measurable parameters are used to model a variety of commercial Ethernet switches. Using parameters measured on real devices, the impact on the overall network performance is modeled. In the ATLAS context, both 100 Mbit and Gigabit Ethernet links are required. A system is described which is capable of characterizing the behavior of commercial switches with the required number of nodes under traffic conditions resembling those to be encountered in the ATLAS experiment. Fast Ethernet traffic is provided by a high density, custom built tester based on FPGAs, programmed in Handel-C and VHDL, while the Gigabit Ethernet traffic is generated using Alteon NICs with custom firmware. The system is currently being deployed with 32 100 Mbit ports and 16 Gigabit ports, and will be expanded to /spl sim/256 nodes of 100 Mbit and /spl sim/50 GBE nodes.en_GB
dc.language.isoenen_GB
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_GB
dc.rightsinfo:eu-repo/semantics/restrictedAccessen_GB
dc.subjectField programmable gate arraysen_GB
dc.subjectComputer simulationen_GB
dc.subjectLocal area networks (Computer networks)en_GB
dc.titleTesting and modeling ethernet switches and networks for use in ATLAS high-level triggersen_GB
dc.typearticleen_GB
dc.rights.holderThe copyright of this work belongs to the author(s)/publisher. The rights of this work are as defined by the appropriate Copyright Legislation or as modified by any successive legislation. Users may access this work and can make use of the information contained in accordance with the Copyright Legislation provided that the author must be properly acknowledged. Further distribution or reproduction in any format is prohibited without the prior permission of the copyright holder.en_GB
dc.description.reviewedpeer-revieweden_GB
dc.identifier.doi10.1109/23.940127-
dc.publication.titleIEEE Transactions on Nuclear Scienceen_GB
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