Please use this identifier to cite or link to this item:
https://www.um.edu.mt/library/oar/handle/123456789/58997
Title: | Hardware implementation of efficient path reconstruction for the Smith-Waterman algorithm |
Authors: | Buhagiar, Karl Casha, Owen Grech, Ivan Gatt, Edward Micallef, Joseph |
Keywords: | Field programmable gate arrays Heuristic algorithms Computer hardware description languages |
Issue Date: | 2017 |
Publisher: | Institute of Electrical and Electronics Engineers |
Citation: | Buhagiar, K., Casha, O., Grech, I., Gatt, E., & Micallef, J. (2017). Hardware implementation of efficient path reconstruction for the Smith-Waterman algorithm. 2017 4th International Conference on Control, Decision and Information Technologies (CoDIT), Barcelona. |
Abstract: | This paper presents the hardware implementation of a differential coded Smith-Waterman algorithm on a field programmable gate array (FPGA). A novel path reconstruction algorithm is proposed to overcome the need of a dedicated memory for the storage of the similarity matrix, thus limiting the on-chip hardware utilization. In addition, this algorithm is also efficient in terms of computational speed since the path reconstruction is carried out during the computation of the similarity score, rather then afterwards, as in the case of the original algorithm. The implementation was done on the Xilinx Spartan-6 XC6LX16-CS324 FPGA using VHDL, consisting of 1,024 processing elements and exhibits a throughput of 204.8 BCUPS at a data rate of 600 Mbps. |
URI: | https://www.um.edu.mt/library/oar/handle/123456789/58997 |
Appears in Collections: | Scholarly Works - FacICTMN |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
Hardware_implementation_of_efficient_path_reconstruction_for_the_Smith-Waterman_algorithm_2017.pdf Restricted Access | 835.21 kB | Adobe PDF | View/Open Request a copy |
Items in OAR@UM are protected by copyright, with all rights reserved, unless otherwise indicated.