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DC Field | Value | Language |
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dc.contributor.author | Seguna, Clive | - |
dc.contributor.author | Gatt, Edward | - |
dc.contributor.author | De Cataldo, Giacinto | - |
dc.contributor.author | Casha, Owen | - |
dc.contributor.author | Grech, Ivan | - |
dc.date.accessioned | 2020-07-27T07:38:45Z | - |
dc.date.available | 2020-07-27T07:38:45Z | - |
dc.date.issued | 2017 | - |
dc.identifier.citation | Clive, S., Gatt, E., De Cataldo, G., Casha, O., & Grech, I. (2017). Proposal for a new ALICE CPV-HMPID front-end electronics topology. 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos. | en_GB |
dc.identifier.uri | https://www.um.edu.mt/library/oar/handle/123456789/59045 | - |
dc.description.abstract | This paper presents the proposal of a new front-end readout electronics (RO) architecture for the ALICE Charged-particle Veto detector (CPV) located in PHOton Spectrometer (PHOS), and for the High Momentum particle IDentification detector (HMPID). With the upgrades in hardware typology and proposed new readout scheme in FPGA design, the RO system shall achieve at least five times the speed of the present front-end readout electronics. Design choices such as using the ALTERA Cyclone V GX FPGA, the topology for parallel readout of Dilogic cards and an upgrade in FPGA design interfaces will enable the RO electronics to reach an approximate interaction rate of 50 kHz. This paper presents the new system hardware as well as the preliminary prototype measurement results. This paper concludes with recommendations for other future planned updates in hardware schema. | en_GB |
dc.language.iso | en | en_GB |
dc.publisher | Institute of Electrical and Electronics Engineers | en_GB |
dc.rights | info:eu-repo/semantics/restrictedAccess | en_GB |
dc.subject | Field programmable gate arrays | en_GB |
dc.subject | Position sensitive particle detectors | en_GB |
dc.subject | Detectors | en_GB |
dc.title | Proposal for a new ALICE CPV-HMPID front-end electronics topology | en_GB |
dc.type | conferenceObject | en_GB |
dc.rights.holder | The copyright of this work belongs to the author(s)/publisher. The rights of this work are as defined by the appropriate Copyright Legislation or as modified by any successive legislation. Users may access this work and can make use of the information contained in accordance with the Copyright Legislation provided that the author must be properly acknowledged. Further distribution or reproduction in any format is prohibited without the prior permission of the copyright holder. | en_GB |
dc.bibliographicCitation.conferencename | 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) | en_GB |
dc.bibliographicCitation.conferenceplace | Giardini Naxos, Italy, 12/15/06/2017 | en_GB |
dc.description.reviewed | peer-reviewed | en_GB |
dc.identifier.doi | 10.1109/PRIME.2017.7974135 | - |
Appears in Collections: | Scholarly Works - FacICTMN |
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Proposal_for_a_new_ALICE_CPV-HMPID_front-end_electronics_topology_2017.pdf Restricted Access | 512.78 kB | Adobe PDF | View/Open Request a copy |
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