Frequency synthesizer architectures for UWB MB OFDM alliance application

Abstract

Ultra Wideband (UWB) is an emerging wireless technology supporting data rates as high as 480 Mb/s. As proposed by the MB-OFDM Alliance, the current frequency spectrum for an UWB communication system ranges from 3.1-to-10.6 GHz divided into 14 bands each with a 528 MHz bandwidth, and are categorised into 5 groups with a strict regulation in emission power of less than -41 dBm as set by the Federal Communications Commission (FCC). The US allows the deployment of UWB systems in the whole frequency band, while Japan, Europe, China and Korea have restricted the use of UWB to a subset of the available frequencies in the US (Batra et al., 2004a). The current frequency plan of the MBOA-UWB system is shown in Fig. 1(a) where the highlighted bands are those deployed in Japan, Europe, China and Korea. An alternative frequency plan is shown in Fig. 1(b) (Mishra et al., 2005). Designing frequency synthesizers for UWB MB-OFDM alliance applications faces particularly stringent challenges and performance criteria. Amongst these one may list the wide range of frequencies to be synthesized, the in-group frequency hopping time (less than 9.5 ns), the reduction of the silicon area and the power consumption in the implementation and the limitation of the integrated spurious tone level in the different bands (less than -32 dBc in a 528 MHz bandwidth). Such challenges cannot be catered for by simply employing standard frequency synthesizer techniques such as a stand alone phase locked loop (Casha et al., 2009a). One of the main objectives of this chapter is to study and compare the current state of the art in frequency synthesis for UWB MBOA applications. On one hand several frequency synthesizers based on single side band frequency mixing will be discussed. These generally require multiple phase-locked loops (PLL), complex dividers and mixers to provide adequate sub-harmonics for the full-band frequency synthesis (Batra et al., 2004b; Mishra et al., 2005). Such architectures are hungry in both silicon area and power consumption. On the other hand, other novel frequency synthesis architectures being investigated as a low silicon area alternative will be included in the discussion. These are either based on delay locked loops (DLL) (Lee & Hsiao, 2005; 2006) or based on phase interpolation direct digital synthesis (DDS) (Casha et al., 2009a). The chapter then discusses a study on such frequency synthesizer architectures with special reference to the investigation of the spurious tone levels at their output. The discussion is aided by means of mathematically derived analysis tools implemented using Matlab. These analytic tools provide an adequate system level simulation with low computational complexity, from which particular design considerations are drawn and are then verified by means of the design and the simulation of actual circuit building blocks using a particular integrated circuit technology. The design considerations focus on the reduction of the spurious tone levels by means of applying different techniques including non-linearity compensation and dynamic element matching techniques. In addition, based on the observations obtained from both the analytic tools and the circuit level simulation, the discussion compares the DLL versus the DDS approach in designing a frequency synthesizer whilst highlighting the advantages and the disadvantages and commenting on the feasibility of the two architectures.