A remotely configurable delay generator for the HMPID L0 trigger

Abstract

This work deals with the design, implementation, and testing of a remotely configurable delay generator which will be used in the High Momentum Particle Identification Detector (HMPID) as part of the LHC-wide upgrade in preparation for Run3 (2021 - 2023). While during the previous two runs (2010 - 2018) HMPID worked with three trigger levels, this will no longer be the case as the triggering mechanism will change. Although HMPID was triggered by the Level-Zero (L0) trigger, which arrives at 1.2µs after an event, this will no longer be the case as the L0 trigger will arrive later. Instead, the Level-Minus (LM) trigger will be used which arrives at 800ns after an event. As such, a delay generator is required such that the trigger signal is delayed by at least 400ns so that the detector is triggered at the peak of the charges on the pads. The work undertaken and described in this dissertation is therefore classified into three parts. The first part relates to the design, implementation, analysis, and testing of a digital delay generator that is based on a shift-register architecture. This delay generator has been implemented on a Xilinx Virtex-5 FPGA and can achieve a delay range of 525ns, with a resolution of 1ns. The second part focuses on the design, analysis, optimisation, and testing of a novel delay generator that is based on a delay locked loop (DLL) architecture that is calibrated in closed loop, and then used in open-loop configuration. While also describing the proposed architecture, this part focuses on the optimisations performed on a symmetric rail-to-rail delay element to maximise linearity. The delay generator was implemented in the X-FAB XH018 technology, and has a range varying from 935ns to 183ns with a resolution of 2ns. Finally, the last part of this work focuses on the firmware upgrades that had to be performed in the detector such that it can handle the new triggering scheme. Through the use of a new firmware architecture, the readout rate of the firmware has been increased from a maximum of 4.57kHz to 14.4kHz, without sacrificing any data integrity.