Design of a high-performance embedded image processing library for EPGA-based reconfigurable platforms

Abstract

Image processing is computationally intensive and often requires significant system resources. High-performance hardware, such as GPUs and high-end CPUs, provide the necessary resources at the cost of high-power requirements. On the other hand, FPGAs are inherently parallel, relatively low power and are particularly suited for image processing because most image processing routines are apt for parallelisation. This thesis treats the design and implementation of a high-performance image processing library intended for embedded image processing applications in VHDL. The project objectives are to design, implement and test an image processing library for use on an FPGA device. Testing was carried out to establish the performance of the design. The parameters of interest are the execution speed, power consumption, cost and FPGA resource-requirements. These give a good idea of the viability of the design for the intended application. This work focuses primarily on convolution-based image filtering because these operations are used frequently and are some of the most demanding in image processing. As a result, they were deemed representative. The design was implemented on an FPGA (Xilinx’s XC7A100TCSG324) using a maximum clock frequency of 232MHz. This significantly outperformed an equivalent implementation using MATLAB®, a matrix-based programming language, optimal for image processing, despite the fact that the MATLAB® implementation was ran on a dual-core CPU operating at a clock speed of 2.2GHz. Compared to the MATLAB® implementation, the FPGA implementation resulted in a shorter execution time of up to 97% for small images and up to 60% for larger images. This despite the fact that the FPGA is running at a clock speed equal to 10.5% of that of the CPU. Furthermore, whereas the CPU used has a power rating of 15W, the FPGA design consumed 0.243W for small images with a size of 64x64 and only increased to 0.269W for larger images of 1920x1080 pixels. For the 1920x1080 pixels image, the implementation consumed only 2958 lookup tables and 2809 flip-flops, small enough to fit on an FPGA such as Xilinx’s XC7S6, which costs only €15.08 (at the time of writing). From this, it was concluded that FPGAs provide a significant advantage over current technology.