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dc.contributor.authorDella Monica, Dario-
dc.contributor.authorFrancalanza, Adrian-
dc.date.accessioned2021-12-28T06:33:45Z-
dc.date.available2021-12-28T06:33:45Z-
dc.date.issued2019-
dc.identifier.citationDella Monica, D., & Francalanza, A. (2019). Pushing runtime verification to the limit : may process semantics be with us. 1st Workshop on Artificial Intelligence and Formal Verification, Logics, Automata and Synthesis (OVERLAY), Rende. 47-52.en_GB
dc.identifier.urihttps://www.um.edu.mt/library/oar/handle/123456789/86108-
dc.description.abstractWe propose a combined approach that permits automated formal verification to be spread across the pre- and post-deployment phases of a system development, with the aim of calibrating the management of the verification burden. Our approach combines standard model checking methods with runtime verification, a relatively novel formal technique that verifies a system during its execution. We carry out our study in terms of the Hennessy-Milner Logic, a branching-time logic for specifying reactive system correctness. Whereas we will be mainly concerned with limiting the model checking verification burden, runtime verification has been shown to handle a strict subset of the expressible properties in our logic of study, posing constraints on what can be shifted to the post-deployment phase. We present a solution, based on modal transition systems and modal refinement, for the fragment of the Hennessy-Milner Logic devoid of recursion, i.e., without least and greatest fixpoint operators.en_GB
dc.description.sponsorshipThis work is partially supported by the Italian INdAM-GNCS project Metodi formali per tecniche di verifica combinata, the Icelandic Research Fund project TheoFoMon: Theoretical Foundations for Monitorability (No.163406-051), and the project BehAPI, funded by the EU H2020 RISE programme under the Marie Skłodowska-Curie grant agreement (No.778233).en_GB
dc.language.isoenen_GB
dc.publisherCEUR Workshop Proceedingsen_GB
dc.rightsinfo:eu-repo/semantics/openAccessen_GB
dc.subjectComputer software -- Verificationen_GB
dc.subjectComputer logicen_GB
dc.subjectComputer software -- Developmenten_GB
dc.subjectSoftware engineeringen_GB
dc.subjectSemanticsen_GB
dc.titlePushing runtime verification to the limit : may process semantics be with usen_GB
dc.typeconferenceObjecten_GB
dc.rights.holderThe copyright of this work belongs to the author(s)/publisher. The rights of this work are as defined by the appropriate Copyright Legislation or as modified by any successive legislation. Users may access this work and can make use of the information contained in accordance with the Copyright Legislation provided that the author must be properly acknowledged. Further distribution or reproduction in any format is prohibited without the prior permission of the copyright holder.en_GB
dc.bibliographicCitation.conferencename1st Workshop on Artificial Intelligence and Formal Verification, Logics, Automata and Synthesis (OVERLAY)en_GB
dc.bibliographicCitation.conferenceplaceRende, Italy, 19-20/11/2019en_GB
dc.description.reviewedpeer-revieweden_GB
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