Hardware implementation of a convolutional encoder with viterbi decoder

Abstract

Since their introduction in 1995 by Elias, Convolutional encoding with Viterbi decoding is a very powerful method for forward error correction. It has been widely exploited in many wireless communication systems to improve the limited capacity of the communications channel. Convolutional codes are also being used as constituent codes in the newest high performance error-control coding Turbo codes. In this thesis a comparison between the different error correcting codes is outlined showing their main advantages, disadvantages and limitations in a communications environment. The different types of Convolutional encoders are also viewed and compared. The Viterbi Algorithm was found to be the most efficient and effective algorithm available to decode such codes. Using software and hardware based simulation software the implementation of a rate V2, constraint length 3 and a memory of 2 Convolutional encoder was simulated and implemented on FPGA. A hard-decision Viterbi decoder was also simulated in software and implemented on an FPGA. Both the encoder and decoder were implemented in hardware as to increase their encoding and decoding speed so as to minimize the delay over a communications channel as much as possible. The implementation on the FPGA also shows the amount of hardware resources that are needed for an efficient error correcting coder.