Compilation for itanium architecture

Abstract

The Itanium Architecture is the first commercial processor architecture based on the explicitly parallel instruction computing (EPIC) paradigm. The performance of code execution on Itanium processors is highly dependent on the quality of the instruction schedule generated by the compiler) since the architecture off-loads traditional hardware functionality to software. This dissertation presents an experimental compiler that exploits specific knowledge of the Itanium architecture to provide an efficient instruction schedule to the hardware. Empirical evaluation shows that the generated code can easily achieve up to 2.5x speed-up over code running on scalar processors. The results of our experiments are encouraging) and present many opportunities for the compiler to be used as a development platform for further research on advanced compiling techniques related to instruction-level parallelism (ILP) and EPIC architectures.