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dc.date.accessioned2022-04-11T13:25:11Z-
dc.date.available2022-04-11T13:25:11Z-
dc.date.issued2014-
dc.identifier.citationCaruana, S. M. (2014). Components for a wavelet based image encoder on FPGA (Bachelor’s dissertation).en_GB
dc.identifier.urihttps://www.um.edu.mt/library/oar/handle/123456789/93382-
dc.descriptionB.Sc. IT (Hons)(Melit.)en_GB
dc.description.abstractData compression is an essential technology in today's world. It helps in the transfer of large amounts of data, mainly caused by either image or video. An existing C++ program which performs image encoding was considered. The objective was to accelerate the major components of the C++ code, on FPGAs. A study of the JPEG 2000 Still Image Compression Standard Development, and ICER Progressive Compression is presented. This explains the different components forming the image encoder, and is essential in understanding the C++ code of the image encoder. The objective of this thesis was to design and implement components for a wavelet based image encoder on an FPGA, which in the future can be used as components in a complete image and video encoding system. First and foremost, a deep analysis of the different components which were written in C++ code, regarding image encoding, was done. Then the task was to implement it in VHDL, which can be used on an FPGA board. Profiling of the C++ code showed that the major component which was first chosen, and built in VHDL code, was the arithmetic encoder. This is so because it was the most used function of the program. The other accompanying components which were also tackled are mainly, the context modelling block: used to determine the particular context of each pixel, the adaptive probability estimator: used to estimate the probabilities of each binary bit; and the bit input and output: used to group bits into bytes. All the mentioned components except the context modelling block were tested rigorously. This was done to conclude that the adaptive probability estimator, the arithmetic encoding and the bit input and output components are working properly. Moreover after implementing the test bench and the top level modules, a post place-and route simulation was made, and the final results were obtained. This means that both the functionality and the timing of the design were tested. By making use of an FPGA accelerator, the amount of process time can be reduced greatly, while maintain the quality of the original compression algorithm.en_GB
dc.language.isoenen_GB
dc.rightsinfo:eu-repo/semantics/restrictedAccessen_GB
dc.subjectData compression (Computer science)en_GB
dc.subjectField programmable gate arraysen_GB
dc.subjectWavelets (Mathematics)en_GB
dc.subjectData compression (Computer science)en_GB
dc.titleComponents for a wavelet based image encoder on FPGAen_GB
dc.typebachelorThesisen_GB
dc.rights.holderThe copyright of this work belongs to the author(s)/publisher. The rights of this work are as defined by the appropriate Copyright Legislation or as modified by any successive legislation. Users may access this work and can make use of the information contained in accordance with the Copyright Legislation provided that the author must be properly acknowledged. Further distribution or reproduction in any format is prohibited without the prior permission of the copyright holder.en_GB
dc.publisher.institutionUniversity of Maltaen_GB
dc.publisher.departmentFaculty of Information and Communication Technology. Department of Communications and Computer Engineeringen_GB
dc.description.reviewedN/Aen_GB
dc.contributor.creatorCaruana, Steve Mauro (2014)-
Appears in Collections:Dissertations - FacICT - 2014
Dissertations - FacICTCCE - 2014

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