Design of a low power successive approximation ADC

Abstract

The spread of technology has created a market for highly developed applications. Such applications are mostly based on mixed signal systems. Thus to interface signals from analogue sensors to digital signal processing units an intermediary device in needed the analogue-to-digital converter (ADC). To accommodate the ever-growing demands different types of ADCs have been reported in literature. The SAR ADC is a common type of converter used for moderate speed/moderate resolution applications which require low power consumption as well as a small form factor. These features make the SAR ideal for implantable biomedical devices and battery operated equipment. This work involves the design of the analogue blocks of the SAR ADC - the DAC and the comparator, using 0.18µ CMOS technology. These components are the main sources of error in the SAR ADC; nevertheless, they need to be highly accurate as the accuracy of the overall system is highly dependent on such components. Moreover, the energy consumed by the switching sequence of the capacitor array in the DAC contributes to the analogue power consumption of the SAR ADC. For these reasons, an analysis of power consumption and errors pertaining to the three fundamental structures of DAC were conducted in this work so as to achieve more accurate components with the least power consumption possible.