Design of a low-voltage multibit Sigma-Delta ADC

Abstract

The evolution of the CMOS technology brought a continuously scaling-down of transistor sizes. Reducing the size of the transistors causes the power supply to decrease and consequently the available voltage swing headroom become limited and designing of integrated circuit become challenging due to the fact that the performance characteristic of the devices degrades. The design of ADC, which interfaces between the analogue world and digital world, is becoming more difficult due to these facts. Many efforts have been made to improve the performances of ADC during the past years. In this thesis Σ-Δ ADC is designed for high resolution and optimum voltage swing solution. First a high level design with MATLAB Simulink is presented, and then circuit level of its building blocks and system level design is considered. Based from the literature review a first-order and second-order 2-bit Σ-Δ modulator is modelled with MATLAB Simulink. The performance characteristics of these modulator's are studied for optimisation and prediction purpose of the circuit level design. The building blocks of Σ-Δ modulators which are, loop filter, 2-bit quantiser, and the feedback DAC are designed using AMS 0.35 µm CMOS technology. A SC integrator is used to design the loop filter, which consist of differential input folded cascode opamp. An opamp is designed and achieved a de gain of 85.59 dB, phase margin 70 degree, GBW 30 MHz, 20 V/µs SR and operates at power supply of 2 V. Using a comparator that operates at 20 MHz a 2-bit flash ADC is designed which is use as a quantiser. Finally at circuit level Σ-Δ modulator is designed using SC DAC and clock generators and simulated in Cadence simulator. The first-order 2-bit Σ-Δ modulator is successfully built and simulated, a system level performance of the modulator is observed and then extended to two 2-bit second-order modulator for optimum noise shaping and high resolution achievement.