Please use this identifier to cite or link to this item:
https://www.um.edu.mt/library/oar/handle/123456789/94485
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.date.accessioned | 2022-04-27T07:25:10Z | - |
dc.date.available | 2022-04-27T07:25:10Z | - |
dc.date.issued | 2010 | - |
dc.identifier.citation | Cefai, I. (2010). Microprocessor operation simulation (Bachelor's dissertation). | en_GB |
dc.identifier.uri | https://www.um.edu.mt/library/oar/handle/123456789/94485 | - |
dc.description | B.SC.(HONS)COMPUTER ENG. | en_GB |
dc.description.abstract | This is the study of a microprocessor operation at clock and instruction level. In this thesis, we present a pedagogical tool. This is the simulation of a microprocessor that could be used in schools, to help in the teaching of the computer architecture and organization. The microprocessor involved is Intel's i486. This simulation shows clearly how the address is composed and how it is used in the processor, to be able to produce some kind of results. This should be only the first part of a bigger project. Here, we are simulating the cache part of the processor. The bigger project includes the implementation of all the other blocks of the processor, so that the simulation would be complete, from fetching the address to the decoding and execution stages of the data. The main aim of this project is to shed light more on the i486 and its cache operation, in particular. The cache is basically used to store recently used data, for quick access to the CPU. The i486 includes an 8Kbyte combined instruction and data cache. This paper will describe the cache's operation and structure in detail. Data (and/or instructions) to the cache can come either from blocks in the processor itself, like Prefetch Unit or the Paging Unit, or else it can come from the external memory through the main bus connecting the CPU to the Main Memory. All this was studied in detail and a graphical simulation was carried out as a final deliverable. This could make it easier to describe how the processor works and by having a visual representation in front of you, the understanding is guaranteed. This project involved a lot of time searching and collecting information on the processor. The approach taken in completing this thesis was firstly to study what the processor (mostly the cache) constituted and then research more on the specific techniques used, from other sources, so as to get to know how the system works. Then, this information was coded in MATLAB which yielded to the simulation of the cache. The results obtained in this project where by applying different addresses to the simulation and then documenting how the program reacted to the address, what approach was taken and if the results were correct or not. | en_GB |
dc.language.iso | en | en_GB |
dc.rights | info:eu-repo/semantics/restrictedAccess | en_GB |
dc.subject | Microprocessors | en_GB |
dc.subject | Computer simulation | en_GB |
dc.subject | MATLAB | en_GB |
dc.title | Microprocessor operation simulation | en_GB |
dc.type | bachelorThesis | en_GB |
dc.rights.holder | The copyright of this work belongs to the author(s)/publisher. The rights of this work are as defined by the appropriate Copyright Legislation or as modified by any successive legislation. Users may access this work and can make use of the information contained in accordance with the Copyright Legislation provided that the author must be properly acknowledged. Further distribution or reproduction in any format is prohibited without the prior permission of the copyright holder. | en_GB |
dc.publisher.institution | University of Malta | en_GB |
dc.publisher.department | Faculty of Information and Communication Technology. Department of Communications and Computer Engineering | en_GB |
dc.description.reviewed | N/A | en_GB |
dc.contributor.creator | Cefai, Isaac (2010) | - |
Appears in Collections: | Dissertations - FacICT - 2010 Dissertations - FacICTCCE - 1999-2013 |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
BSC(HONS)ICT_Cefai_Isaac_2010.PDF Restricted Access | 7.68 MB | Adobe PDF | View/Open Request a copy | |
Cefai_Isaac_acc.material.pdf Restricted Access | 215.42 kB | Adobe PDF | View/Open Request a copy |
Items in OAR@UM are protected by copyright, with all rights reserved, unless otherwise indicated.