Radiation-hardening-by-design of integrated circuits

Abstract

The scope of this project is to investigate digital integrated circuits (ICs) fabricated in standard CMOS technology which are able to withstand radiation effects, through the use of voting logic circuitry and error checking systems, aimed at reducing single event effects. In a radiation environment, where I Cs perform critical functionalities, high-energy ions can penetrate ICs and cause temporary upsets and, in extreme cases, also permanent damage. One important set of errors that can result from incident radiation in digital I Cs relates to single-event effects (SEE), the most frequent of which are single-event upsets (SEU) and single-event transients (SET). The approach used in this project to mitigate radiation-induced SEU, is decision making through voting logic circuitry using what is known as Triple Modular Redundancy (TMR). A unanimous circuit and a self-testing circuit have also been investigated in conjunction with the voting circuitry approach in order to provide a more efficient and reliable hardened device. In order to mitigate SET temporal offsets have also been added to eliminate any transient that can result on the data lines. The use of error checking on important blocks is needed to cater for the rare coincidence of having more than one error on the same circuit block. In the case of memories, instead of the TMR approach, an error correction code has been implemented in order to detect and correct bit errors due to SEUs on memory locations. Several simulations on different digital blocks were performed to ensure the correct operation of the circuits by considering all possible outcomes and that the correct output is produced.