Please use this identifier to cite or link to this item:
https://www.um.edu.mt/library/oar/handle/123456789/17632| Title: | Artificial neural network optimization for FPGA |
| Authors: | Bonnici, Mark Gatt, Edward Micallef, Joseph Grech, Ivan |
| Keywords: | Field programmable gate arrays Neural networks (Computer science) Computer hardware description languages |
| Issue Date: | 2006 |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Citation: | Bonnici, M., Gatt, E., Micallef, J., & Grech, I. (2006). Artificial neural network optimization for FPGA. 13th IEEE International Conference on Electronics, Circuits and Systems, Nice. 1340-1343. |
| Abstract: | This paper describes a cost effective artificial neural network implementation on an FPGA in three easy steps. Furthermore, it proposes the manner in which network layers are mapped into a particular hardware structure such that the performance and efficiency, with which the hardware resources are used, are greatly improved. A reconfigurable, parameterised neural node is presented as the basic building block for neural implementations, and is modelled in Verilog (HDL). The results show a high degree of parallelism, fast performance and most important low area resources. |
| URI: | https://www.um.edu.mt/library/oar//handle/123456789/17632 |
| Appears in Collections: | Scholarly Works - FacICTMN |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Artificial Neural Network Optimization for FPGA.pdf Restricted Access | Artificial neural network optimization for FPGA | 276.81 kB | Adobe PDF | View/Open Request a copy |
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