Front-end readout electronics for the ALICE CPV and HMPID particle detectors

Abstract

This work, carried out in collaboration with the European Council for Nuclear Research (CERN) and the University of Malta, presents the development of a new electronic front-end readout system for the High momentum particle identification (HMPID) and Charged Particle Veto (CPV) detectors. The upgrade strategy of the A Large Ion Collider Experiment (ALICE) is based on the collection of more than 10 nb-1 Pb-Pb collisions at a luminosity of 6x1027 cm-2 8 -1, corresponding to a collision rate of 50 kHz for Pb-Pb and 200 kHz for pp and p-Pb. The requirements for such a high beam luminosity cannot be met with the existing CPV electronics, which had a low readout rate of 5 kHz. The development of such a system is a challenging task. Therefore, different technologies and architectural topologies were considered and investigated for the optimization of the front-end readout electronics. This work contributed to the development of a new custom front-end readout electronics system architecture for the CPV detector module in the PHOton spectrometer (PHOS). This newly developed electronics were commissioned and accepted by the Russian Institute of High Energy Physics and the ALICE collaboration for installation in November 2020. Compared to previous systems, the proposed new architecture allows parallel readout and processing of all 480 silicon photomultiplier pads connected to digital signal processing boards. Optimization strategies include the use of 28 nm FPGA technology with high pin count and low power consumption for simultaneous readout of digital signal processors, referred to as 5 DIL boards, and the use of high-speed 3.125 Gbps transceiver interconnects. In addition, the newly developed FPGA firmware architecture has helped increase the event readout rate and data throughput by a factor of ten. This work enables both the CPV and HMPID detectors to achieve an interaction rate of at least 50 kHz. The system design consists of three modules, each containing two segment cards, two readout common boards (RCBs), and 20 digital signal processors. Five processors are grouped on an electronic board called 5- DIL board. This report presents the architectural layout and preliminary results of performance measurements for the proposed new design. In addition, this work has contributed to the development of a new ASIC chip that integrates four digital signal processors, error correction and detection circuitry, and four serial transmitters with a bandwidth of at least 0.5 Gbps. The ASIC chip implementation uses XFAB-180-nm technology and is capable of processing at least 192 analogue channels simultaneously. The developed ASIC device can be easily integrated into current CPV and similar electronic readout circuits for physics particle detectors, which helps reduce the required number of electronic components and PCB manufacturing costs. This work concludes with recommendations for further planned updates to the hardware scheme.