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DC Field | Value | Language |
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dc.contributor.author | Zarb, Terence | - |
dc.contributor.author | Grech, Ivan | - |
dc.contributor.author | Gatt, Edward | - |
dc.contributor.author | Casha, Owen | - |
dc.contributor.author | Micallef, Joseph | - |
dc.date.accessioned | 2017-03-26T17:47:24Z | - |
dc.date.available | 2017-03-26T17:47:24Z | - |
dc.date.issued | 2011 | - |
dc.identifier.citation | Zarb, T., Grech, I., Gatt, E., Casha, O., & Micallef, J. (2011). Verification of a VHDL GPS baseband processor using a simulink-based test bench generator. 17th IEEE International Conference on Electronics, Circuits and Systems, Athens. 327-330. | en_GB |
dc.identifier.uri | https://www.um.edu.mt/library/oar//handle/123456789/17829 | - |
dc.description.abstract | In the last decades, Global Positioning System (GPS) receivers have become more popular and are now incorporated in mobile phone electronics and also in navigation systems, namely in automotive, marine and aerospace equipment. This paper presents the design of various digital signal processing (DSP) and communication blocks which form an integral part of a typical L1-band Coarse/Acquisition (C/A)-code baseband receiver. These modules are designed using synthesizable VHDL code and implemented on a Field Programmable Gate Array (FPGA). Furthermore, a novel satellite signal modulation model is also designed to model how signals are generated by the satellites. This is designed to ultimately generate the VHDL test-bench to verify the functionality of the designed receiver. This model can be extended to cater for second order effects such as Doppler shifts, atmospheric delays and weather conditions. In this work, the noise performance of the receiver is analyzed. It is noted that the minimum signal-to-noise ratio (SNR) that the baseband processor can tolerate is −10 dB given a correlation window of 2 ms. | en_GB |
dc.language.iso | en | en_GB |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_GB |
dc.rights | info:eu-repo/semantics/restrictedAccess | en_GB |
dc.subject | Global Positioning System | en_GB |
dc.subject | Field programmable gate arrays | en_GB |
dc.subject | Radio frequency modulation | en_GB |
dc.subject | Artificial satellites in telecommunication | en_GB |
dc.title | Verification of a VHDL GPS baseband processor using a simulink-based test bench generator | en_GB |
dc.type | conferenceObject | en_GB |
dc.rights.holder | The copyright of this work belongs to the author(s)/publisher. The rights of this work are as defined by the appropriate Copyright Legislation or as modified by any successive legislation. Users may access this work and can make use of the information contained in accordance with the Copyright Legislation provided that the author must be properly acknowledged. Further distribution or reproduction in any format is prohibited without the prior permission of the copyright holder. | en_GB |
dc.bibliographicCitation.conferencename | 17th IEEE International Conference on Electronics, Circuits and Systems | en_GB |
dc.bibliographicCitation.conferenceplace | Athens, Greece, 12-15/12/2010 | en_GB |
dc.description.reviewed | peer-reviewed | en_GB |
dc.identifier.doi | 10.1109/ICECS.2010.5724519 | - |
Appears in Collections: | Scholarly Works - FacICTMN |
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File | Description | Size | Format | |
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VERIFICATION OF A VHDL GPS BASEBAND PROCESSOR USING A SIMULINK-BASED TEST BENCH GENERATOR.pdf Restricted Access | Verification of a VHDL GPS baseband processor using a simulink-based test bench generator | 764.76 kB | Adobe PDF | View/Open Request a copy |
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